Low Density Parity Check (LDPC) codes have been adopted in a number of wired and wireless communication standards due to their improved error correcting ability and relatively simple decoder structure. However, for very high throughput systems operating in the multi-Gb/s range conventional decoding methods based on message passing are limited, due largely to the sheer volume of messages being exchanged. Thus, simpler decoding methods have been proposed such as bit flipping permitting efficient and fast hardware implementation. This paper presents two new bit flipping algorithm designed to reduce latency and power consumption. For a small loss in bit error rate performance (0.5 dB) we show how the application of an early stopping criteria uses 89% fewer iterations compared to a similar published algorithm. We also present a method for reducing power consumption by placing processing elements into a quiescent state based on a bit-local metric. Using this technique we show a potential reduction in power consumption of 76%.
|Translated title of the contribution||Low latency low power bit flipping algorithms for LDPC decoding|
|Title of host publication||IEEE 21st International Symposium on Personal, Indoor and Mobile Radio Communications 2010 (PIMRC 2010), Istanbul, Turkey|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Pages||278 - 282|
|Number of pages||4|
|Publication status||Published - Sep 2010|
|Event||21st International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC) - Istanbul, Turkey|
Duration: 1 Sep 2010 → …
|Conference||21st International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)|
|Period||1/09/10 → …|
Bibliographical noteRose publication type: Conference contribution
Sponsorship: The authors would like to thank Toshiba TRL and its directors for supporting this work.
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- LDPC decoding