Low latency low power bit flipping algorithms for LDPC decoding

MR Ismail; I Ahmed; JP Coon; SMD Armour; T Koçak; JP McGeehan

doi:10.1109/PIMRC.2010.5671820

Low latency low power bit flipping algorithms for LDPC decoding

MR Ismail, I Ahmed, JP Coon, SMD Armour, T Koçak, JP McGeehan

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

16 Citations (Scopus)

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Abstract

Low Density Parity Check (LDPC) codes have been adopted in a number of wired and wireless communication standards due to their improved error correcting ability and relatively simple decoder structure. However, for very high throughput systems operating in the multi-Gb/s range conventional decoding methods based on message passing are limited, due largely to the sheer volume of messages being exchanged. Thus, simpler decoding methods have been proposed such as bit flipping permitting efficient and fast hardware implementation. This paper presents two new bit flipping algorithm designed to reduce latency and power consumption. For a small loss in bit error rate performance (0.5 dB) we show how the application of an early stopping criteria uses 89% fewer iterations compared to a similar published algorithm. We also present a method for reducing power consumption by placing processing elements into a quiescent state based on a bit-local metric. Using this technique we show a potential reduction in power consumption of 76%.

Translated title of the contribution	Low latency low power bit flipping algorithms for LDPC decoding
Original language	English
Title of host publication	IEEE 21st International Symposium on Personal, Indoor and Mobile Radio Communications 2010 (PIMRC 2010), Istanbul, Turkey
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	278 - 282
Number of pages	4
ISBN (Print)	9781424480159
DOIs	https://doi.org/10.1109/PIMRC.2010.5671820
Publication status	Published - Sept 2010
Event	21st International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC) - Istanbul, Turkey Duration: 1 Sept 2010 → …

Conference

Conference	21st International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)
Country/Territory	Turkey
City	Istanbul
Period	1/09/10 → …

Bibliographical note

Rose publication type: Conference contribution

Sponsorship: The authors would like to thank Toshiba TRL and its directors for supporting this work.

Terms of use: Copyright © 2010 IEEE. Reprinted from IEEE 21st International Symposium on Personal, Indoor and Mobile Radio Communications 2010 (PIMRC 2010).

This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected].

By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

Keywords

LDPC decoding

Access to Document

10.1109/PIMRC.2010.5671820

Ismail IEEE PIMRC 2010Accepted author manuscript, 304 KB

http://hdl.handle.net/1983/1710

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Ismail, MR., Ahmed, I., Coon, JP., Armour, SMD., Koçak, T., & McGeehan, JP. (2010). Low latency low power bit flipping algorithms for LDPC decoding. In IEEE 21st International Symposium on Personal, Indoor and Mobile Radio Communications 2010 (PIMRC 2010), Istanbul, Turkey (pp. 278 - 282). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/PIMRC.2010.5671820

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abstract = "Low Density Parity Check (LDPC) codes have been adopted in a number of wired and wireless communication standards due to their improved error correcting ability and relatively simple decoder structure. However, for very high throughput systems operating in the multi-Gb/s range conventional decoding methods based on message passing are limited, due largely to the sheer volume of messages being exchanged. Thus, simpler decoding methods have been proposed such as bit flipping permitting efficient and fast hardware implementation. This paper presents two new bit flipping algorithm designed to reduce latency and power consumption. For a small loss in bit error rate performance (0.5 dB) we show how the application of an early stopping criteria uses 89\% fewer iterations compared to a similar published algorithm. We also present a method for reducing power consumption by placing processing elements into a quiescent state based on a bit-local metric. Using this technique we show a potential reduction in power consumption of 76\%.",

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author = "MR Ismail and I Ahmed and JP Coon and SMD Armour and T Ko{\c c}ak and JP McGeehan",

note = "Rose publication type: Conference contribution Sponsorship: The authors would like to thank Toshiba TRL and its directors for supporting this work. Terms of use: Copyright {\textcopyright} 2010 IEEE. Reprinted from IEEE 21st International Symposium on Personal, Indoor and Mobile Radio Communications 2010 (PIMRC 2010). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected]. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. ; 21st International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC) ; Conference date: 01-09-2010",

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Ismail, MR, Ahmed, I, Coon, JP, Armour, SMD, Koçak, T & McGeehan, JP 2010, Low latency low power bit flipping algorithms for LDPC decoding. in IEEE 21st International Symposium on Personal, Indoor and Mobile Radio Communications 2010 (PIMRC 2010), Istanbul, Turkey. Institute of Electrical and Electronics Engineers (IEEE), pp. 278 - 282, 21st International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), Istanbul, Turkey, 1/09/10. https://doi.org/10.1109/PIMRC.2010.5671820

Low latency low power bit flipping algorithms for LDPC decoding. / Ismail, MR; Ahmed, I; Coon, JP et al.
IEEE 21st International Symposium on Personal, Indoor and Mobile Radio Communications 2010 (PIMRC 2010), Istanbul, Turkey. Institute of Electrical and Electronics Engineers (IEEE), 2010. p. 278 - 282.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

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AU - Koçak, T

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N1 - Rose publication type: Conference contribution Sponsorship: The authors would like to thank Toshiba TRL and its directors for supporting this work. Terms of use: Copyright © 2010 IEEE. Reprinted from IEEE 21st International Symposium on Personal, Indoor and Mobile Radio Communications 2010 (PIMRC 2010). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected]. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

PY - 2010/9

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N2 - Low Density Parity Check (LDPC) codes have been adopted in a number of wired and wireless communication standards due to their improved error correcting ability and relatively simple decoder structure. However, for very high throughput systems operating in the multi-Gb/s range conventional decoding methods based on message passing are limited, due largely to the sheer volume of messages being exchanged. Thus, simpler decoding methods have been proposed such as bit flipping permitting efficient and fast hardware implementation. This paper presents two new bit flipping algorithm designed to reduce latency and power consumption. For a small loss in bit error rate performance (0.5 dB) we show how the application of an early stopping criteria uses 89% fewer iterations compared to a similar published algorithm. We also present a method for reducing power consumption by placing processing elements into a quiescent state based on a bit-local metric. Using this technique we show a potential reduction in power consumption of 76%.

AB - Low Density Parity Check (LDPC) codes have been adopted in a number of wired and wireless communication standards due to their improved error correcting ability and relatively simple decoder structure. However, for very high throughput systems operating in the multi-Gb/s range conventional decoding methods based on message passing are limited, due largely to the sheer volume of messages being exchanged. Thus, simpler decoding methods have been proposed such as bit flipping permitting efficient and fast hardware implementation. This paper presents two new bit flipping algorithm designed to reduce latency and power consumption. For a small loss in bit error rate performance (0.5 dB) we show how the application of an early stopping criteria uses 89% fewer iterations compared to a similar published algorithm. We also present a method for reducing power consumption by placing processing elements into a quiescent state based on a bit-local metric. Using this technique we show a potential reduction in power consumption of 76%.

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BT - IEEE 21st International Symposium on Personal, Indoor and Mobile Radio Communications 2010 (PIMRC 2010), Istanbul, Turkey

PB - Institute of Electrical and Electronics Engineers (IEEE)

T2 - 21st International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)

Y2 - 1 September 2010

ER -

Low latency low power bit flipping algorithms for LDPC decoding

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Keywords

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