Projects per year
technique for third-order intercept point (IP3) improvement in
low noise amplifiers (LNAs). The proposed LNA is designed
for mid-band 5G (3-4GHz) wireless receivers and it is based
on a cascode topology. An auxiliary transistor provides a
feedforward correction path for third-order intermodulation
(IM3) cancellation. The effects of the second harmonic on the IM3
are also considered in the modelling. Theoretical and simulation
analysis of the circuit result in a DC power consumption of
306mW from a supply voltage of 3V, an OIP3 of 30.8dBm, noise
figure (NF) of 0.94dB and 13.8dB of power gain are obtained.
The LNA is simulated for a hybrid circuit implementation using
a 400um GaAs packaged transistor.
|Title of host publication||2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Number of pages||4|
|Publication status||Published - 29 Dec 2020|
- Logic gates
- Noise measurement
- Radio frequency
- fifth-generation (5G)
- low noise amplifier
- third-order intercept point (IP3)
- third-order intermodulation (IM3)
FingerprintDive into the research topics of 'Low-Noise Amplifier with Wideband Feedforward Linearisation for Mid-Band 5G Receivers'. Together they form a unique fingerprint.
- 1 Active
Beach, M. A., Chin, W. H., Morris, K. A., Hilton, G., Armour, S. M. D., Haine, J. L., Rogoyski, A., Wales, S. W., Zhu, Z., Watkins, G. T., Cappello, T., Kalokidou, V., Arabi, E., Nair, M., Ma, J., Wilson, S., Ozan, S. H. O. & Prior, R. E.
1/02/20 → 31/01/25