Low Power and Robust Binary Tree SRAM Design for Embedded Systems: 2013 International Symposium on Electronic System Design

Low power consumption is a prime design requirement
for modern embedded systems memories. However,
low power design of these memories is highly challenging due
to conflicting design requirements of high-performance and
robustness under process-voltage-temperature (PVT) variations.
In this paper, we propose a novel low power high-performance
static random access memory (LPSRAM) design. In our proposed
LPSRAM design, we divide the SRAM subsystem into modules,
with inter-module connections organized in a binary tree. We
show that due to such organization LPSRAM can benefit from
low power consumption and dynamic reconfiguration during
normal operational mode. Moreover, during test mode most of
the SRAM cells can be switched off to provide with substantial
leakage power reduction.We formulate the energy and read/write
performance models of the proposed memory design, which
are then substantiated and validated through a number of
experiments using CAD tools and HSPICE simulations. We show
that LPSRAM can significantly reduce power consumption (by
up to 30% in normal operational mode and by approximately 90%
during test mode) when compared with traditional SRAM designs
at the expense of reasonable area overheads. Furthermore, we
demonstrate that due to efficient switching architecture LPSRAM
offers better robustness under process variations, while retaining
high performance.