To date, all of the proposals for low-power designs of RAMs essentially focus on circuit-level solutions. What we propose here is a novel architecture (high) level solution. Our methodology provides a systematic tradeoff between power and area. Also, it allows tradeoff between test time and power consumed in test mode. Significantly, too, the proposed design has the potential to achieve performance improvements while simultaneously reducing power. In this respect, it stands apart from other approaches where power reduction results in speed reduction. The basic approach here divides the RAM into modules, interconnecting these modules in a binary tree where the tree can be reconfigured dynamically during normal operation and during test mode. Furthermore, during test mode, most of the RAM can be switched off, which provides major power reduction, while test-application time is reduced. The aspect ratio of the modules is allowed to vary as a design parameter. The chosen aspect ratio for module impacts power/access time/area tradeoffs. Such novel features make the proposed methodology of potential practical significance. Also, a design tool is developed which inputs various parameters, such as desired power/performance, giving outputs basic design parameters, such as the needed number of modules, area overhead, and resulting test speed-up.
|Translated title of the contribution||LPRAM: a novel low-power high-performance RAM design with testability and scalability|
|Pages (from-to)||637 - 651|
|Number of pages||14|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|Publication status||Published - May 2004|
Bibliographical notePublisher: Institute of Electrical and Electronics Engineers