Matrix codes for reliable and cost efficient memory chips

Costas Argyrides, Dhiraj K Pradhan, Taskin Kocak

Research output: Contribution to journalArticle (Academic Journal)peer-review

72 Citations (Scopus)

Abstract

This paper presents a method to protect memories against multiple bit upsets and to improve manufacturing yield. The proposed method, called a Matrix code, combines Hamming and Parity codes to assure the improvement of reliability and yield of the memory chips in the presence of high defects and multiple bit-upsets. The method is evaluated using fault injection experiments. The results are compared to well-known techniques such as Reed–Muller and Hamming codes. The proposed technique performs better than the Hamming codes and achieves comparable performance with Reed–Muller codes with very favorable implementation gains such as 25% reduction in area and power consumption. It also achieves reliability increase by more than 50% in some cases. Further, the yield benefits provided by the proposed method, measured by the yield improvements per cost metric, is up to 300% better than the ones provided by Reed–Muller codes.
Translated title of the contributionMatrix codes for reliable and cost efficient memory chips
Original languageEnglish
Pages (from-to)1 - 9
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume19
Issue number3
DOIs
Publication statusPublished - Jul 2011

Bibliographical note

Publisher: IEEE

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