| Translated title of the contribution | Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories |
|---|---|
| Original language | English |
| Title of host publication | 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07) |
| Publication status | Published - 2007 |
Bibliographical note
Other page information: -Conference Proceedings/Title of Journal: 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07)
Other identifier: 2000733
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