Maximizing Throughput over Parallel Wire Structures in the Deep Submicrometer Regime

Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen

Research output: Contribution to journalArticle (Academic Journal)peer-review

67 Citations (Scopus)

Abstract

In a parallel multiwire structure, the exact spacing and size of the wires determine both the resistance and the distribution of the capacitance between the ground plane and the adjacent signal carrying conductors, and have a direct effect on the delay. Using closed-form equations that map the geometry to the wire parasitics and empirical switch factor based delay models that show how repeaters can be optimized to compensate for dynamic effects, we devise a method of analysis for optimizing throughput over a given metal area. This analysis is used to show that there is a clear optimum configuration for the wires which maximizes the total bandwidth. Additionally, closed form equations are derived, the roots of which give close to optimal solutions. It is shown that for wide buses, the optimal wire width and spacing are independent of the total width of the bus, allowing easy optimization of on-chip buses. Our analysis and results are valid for lossy interconnects as are typical of wires in submicron technologies.
Original languageUndefined/Unknown
Pages (from-to)224-243
Number of pages20
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume11
Issue number2
DOIs
Publication statusPublished - 1 Apr 2003

Keywords

  • VLSI
  • capacitance
  • circuit optimisation
  • crosstalk
  • delay estimation
  • integrated circuit interconnections
  • integrated circuit layout
  • integrated circuit modelling
  • transmission line theory
  • bandwidth maximization
  • closed-form equations
  • deep submicron regime
  • dynamic effects compensation
  • empirical switch factor based delay models
  • ground plane
  • high-speed interconnect
  • interconnect delay
  • lossy interconnects
  • on-chip bus
  • optimum configuration
  • parallel multiwire structure
  • parallel wire structures
  • repeater insertion
  • repeater optimization
  • signal carrying conductors
  • throughput maximization
  • wire optimization
  • wire parasitics
  • Conductors
  • Delay effects
  • Equations
  • Geometry
  • Optimization methods
  • Parasitic capacitance
  • Solid modeling
  • Switches
  • Throughput
  • Wire

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