Memory Technology for Extended Large-Scale Integration in Future Electronics Applications

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

2 Citations (Scopus)

Abstract

Extending 2-D planar topologies in integrated circuits (ICs) to a 3-D implementation has the obvious benefits of reducing the overall footprint and average interconnection length, with associated improvements in cost, and delay and energy consumption, while also providing an opportunity to integrate disparate technologies. Such advances are very much technology driven, and early research into 3-D integration has now crystallised into commercially viable options that are being pursued by many companies. Being able to position memory in closer proximity to processing elements in a NoC architecture as afforded by a 3-D physical architecture has the potential to improve the memory bandwidth and mitigate the general nature of delay constrained performance in IC design. Understanding the nature of the opportunities and constraints provided in such a 3-D physical architecture is crucial in realising the true benefits of 3-D integration in future applications.
Original languageUndefined/Unknown
Title of host publicationProc. Design, Automation and Test in Europe Conference (DATE)
Pages1126-1127
Number of pages2
DOIs
Publication statusPublished - 1 Mar 2008

Bibliographical note

Invited Presentation, Hot Topic Session

Keywords

  • integrated circuit technology
  • integrated memory circuits
  • large scale integration
  • network-on-chip
  • 2D planar topologies
  • 3D integrated circuits
  • 3D physical architecture
  • IC design
  • NoC architecture
  • energy consumption
  • integrated circuits
  • large-scale integration
  • memory technology
  • Bandwidth
  • Circuit topology
  • Costs
  • Crystallization
  • Delay
  • Energy consumption
  • Integrated circuit interconnections
  • Integrated circuit technology
  • Large scale integration
  • Network-on-a-chip

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