Abstract
Recently a mathematical framework was presented that bridges the gap between bit level BDD representation and word level representations such as BMD and TED. Here we present an approach that demonstrates that these diagrams admit fast evaluation of circuits for multiple outputs. The representation is based on characteristic function which provides faster evaluation time as well as compact representation. The average path length is used as a metric for evaluation time. The results obtained for benchmark circuits shows lesser number of nodes and faster evaluation time compared to binary representation
| Translated title of the contribution | MODD for CF: a representation for fast evaluation of multiple-output functions |
|---|---|
| Original language | English |
| Pages (from-to) | 61 - 66 |
| Number of pages | 5 |
| Journal | Ninth IEEE International High-Level Design Validation and Test Workshop, 2004. |
| Publication status | Published - Nov 2004 |