Modeling the Computational Efficiency of 2-D and 3-D Silicon Processors for Early Chip Planning

Grange M., Jantsch A., Weerasekera R., D Pamunuwa

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

3 Citations (Scopus)


Hierarchical models from physical to system-level are proposed for architectural exploration of high-performance silicon systems to quantify the performance and cost trade offs for 2-D and 3-D IC implementations. We show that 3-D systems can reduce interconnect delay and energy by up to an order of magnitude over 2-D, with an increase of 20-30% in performance-per-watt for every doubling of stack height. Contrary to previous analysis, the improved energy efficiency is achievable at a favorable cost. The models are packaged as a standalone tool and can provide fast estimation of coarse-grain performance and cost limitations for a variety of processing systems to be used at the early chip-planning phase of the design cycle.
Original languageEnglish
Title of host publicationInternational Conference on Computer-Aided Design (ICCAD), San Jose CA, USA
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages8
ISBN (Electronic)978-1-4577-1398-9
ISBN (Print)978-1-4577-1399-6
Publication statusPublished - 10 Nov 2011

Publication series

NameComputer-Aided Design (ICCAD)
ISSN (Print)1092-3152

Bibliographical note

Conference Organiser: IEEE/ACM


  • elemental semiconductors
  • integrated circuit interconnections
  • integrated circuit modelling
  • silicon
  • three-dimensional integrated circuits
  • 2D IC
  • 2D silicon processors
  • 3D IC
  • 3D silicon processors
  • Si
  • early-chip planning
  • energy efficiency
  • interconnect delay
  • processing systems
  • Computational modeling
  • Integrated circuit modeling
  • Program processors
  • Random access memory
  • System-on-a-chip
  • Topology
  • Wires


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