Modeling the Computational Efficiency of 2-D and 3-D Silicon Processors for Early Chip Planning

Matthew Grange; Axel Jantsch; Roshan Weerasekera; Dinesh Pamunuwa

doi:10.1109/ICCAD.2011.6105347

Modeling the Computational Efficiency of 2-D and 3-D Silicon Processors for Early Chip Planning

Matthew Grange, Axel Jantsch, Roshan Weerasekera, Dinesh Pamunuwa

Microelectronics

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

3 Citations (Scopus)

Abstract

Hierarchical models from physical to system-level are proposed for architectural exploration of high-performance silicon systems to quantify the performance and cost trade offs for 2-D and 3-D IC implementations. We show that 3-D systems can reduce interconnect delay and energy by up to an order of magnitude over 2-D, with an increase of 20-30% in performance-per-watt for every doubling of stack height. Contrary to previous analysis, the improved energy efficiency is achievable at a favorable cost. The models are packaged as a standalone tool and can provide fast estimation of coarse-grain performance and cost limitations for a variety of processing systems to be used at the early chip-planning phase of the design cycle.

Original language	English
Title of host publication	2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	310-317
Number of pages	8
ISBN (Electronic)	978-1-4577-1398-9
ISBN (Print)	978-1-4577-1399-6
DOIs	https://doi.org/10.1109/ICCAD.2011.6105347
Publication status	Published - 10 Nov 2011

Publication series

Name	Computer-Aided Design (ICCAD)
ISSN (Print)	1092-3152

Bibliographical note

Conference Organiser: IEEE/ACM

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Research Groups and Themes

Photonics and Quantum

Keywords

elemental semiconductors
integrated circuit interconnections
integrated circuit modelling
silicon
three-dimensional integrated circuits
2D IC
2D silicon processors
3D IC
3D silicon processors
Si
early-chip planning
energy efficiency
interconnect delay
processing systems
Computational modeling
Integrated circuit modeling
Program processors
Random access memory
System-on-a-chip
Topology
Wires

Access to Document

10.1109/ICCAD.2011.6105347

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Cite this

Grange, M., Jantsch, A., Weerasekera, R., & Pamunuwa, D. (2011). Modeling the Computational Efficiency of 2-D and 3-D Silicon Processors for Early Chip Planning. In 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (pp. 310-317). (Computer-Aided Design (ICCAD)). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/ICCAD.2011.6105347

@inproceedings{cd9b42e71cf04fa889e32418ba2e6507,

title = "Modeling the Computational Efficiency of 2-D and 3-D Silicon Processors for Early Chip Planning",

abstract = "Hierarchical models from physical to system-level are proposed for architectural exploration of high-performance silicon systems to quantify the performance and cost trade offs for 2-D and 3-D IC implementations. We show that 3-D systems can reduce interconnect delay and energy by up to an order of magnitude over 2-D, with an increase of 20-30\% in performance-per-watt for every doubling of stack height. Contrary to previous analysis, the improved energy efficiency is achievable at a favorable cost. The models are packaged as a standalone tool and can provide fast estimation of coarse-grain performance and cost limitations for a variety of processing systems to be used at the early chip-planning phase of the design cycle.",

keywords = "elemental semiconductors, integrated circuit interconnections, integrated circuit modelling, silicon, three-dimensional integrated circuits, 2D IC, 2D silicon processors, 3D IC, 3D silicon processors, Si, early-chip planning, energy efficiency, interconnect delay, processing systems, Computational modeling, Integrated circuit modeling, Program processors, Random access memory, System-on-a-chip, Topology, Wires",

author = "Matthew Grange and Axel Jantsch and Roshan Weerasekera and Dinesh Pamunuwa",

note = "Conference Organiser: IEEE/ACM",

year = "2011",

month = nov,

day = "10",

doi = "10.1109/ICCAD.2011.6105347",

language = "English",

isbn = "978-1-4577-1399-6",

series = "Computer-Aided Design (ICCAD)",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

pages = "310--317",

booktitle = "2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)",

address = "United States",

}

Grange, M, Jantsch, A, Weerasekera, R & Pamunuwa, D 2011, Modeling the Computational Efficiency of 2-D and 3-D Silicon Processors for Early Chip Planning. in 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). Computer-Aided Design (ICCAD), Institute of Electrical and Electronics Engineers (IEEE), pp. 310-317. https://doi.org/10.1109/ICCAD.2011.6105347

Modeling the Computational Efficiency of 2-D and 3-D Silicon Processors for Early Chip Planning. / Grange, Matthew; Jantsch, Axel; Weerasekera, Roshan et al.
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). Institute of Electrical and Electronics Engineers (IEEE), 2011. p. 310-317 (Computer-Aided Design (ICCAD)).

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - Modeling the Computational Efficiency of 2-D and 3-D Silicon Processors for Early Chip Planning

AU - Grange, Matthew

AU - Jantsch, Axel

AU - Weerasekera, Roshan

AU - Pamunuwa, Dinesh

N1 - Conference Organiser: IEEE/ACM

PY - 2011/11/10

Y1 - 2011/11/10

N2 - Hierarchical models from physical to system-level are proposed for architectural exploration of high-performance silicon systems to quantify the performance and cost trade offs for 2-D and 3-D IC implementations. We show that 3-D systems can reduce interconnect delay and energy by up to an order of magnitude over 2-D, with an increase of 20-30% in performance-per-watt for every doubling of stack height. Contrary to previous analysis, the improved energy efficiency is achievable at a favorable cost. The models are packaged as a standalone tool and can provide fast estimation of coarse-grain performance and cost limitations for a variety of processing systems to be used at the early chip-planning phase of the design cycle.

AB - Hierarchical models from physical to system-level are proposed for architectural exploration of high-performance silicon systems to quantify the performance and cost trade offs for 2-D and 3-D IC implementations. We show that 3-D systems can reduce interconnect delay and energy by up to an order of magnitude over 2-D, with an increase of 20-30% in performance-per-watt for every doubling of stack height. Contrary to previous analysis, the improved energy efficiency is achievable at a favorable cost. The models are packaged as a standalone tool and can provide fast estimation of coarse-grain performance and cost limitations for a variety of processing systems to be used at the early chip-planning phase of the design cycle.

KW - elemental semiconductors

KW - integrated circuit interconnections

KW - integrated circuit modelling

KW - silicon

KW - three-dimensional integrated circuits

KW - 2D IC

KW - 2D silicon processors

KW - 3D IC

KW - 3D silicon processors

KW - Si

KW - early-chip planning

KW - energy efficiency

KW - interconnect delay

KW - processing systems

KW - Computational modeling

KW - Integrated circuit modeling

KW - Program processors

KW - Random access memory

KW - System-on-a-chip

KW - Topology

KW - Wires

U2 - 10.1109/ICCAD.2011.6105347

DO - 10.1109/ICCAD.2011.6105347

M3 - Conference Contribution (Conference Proceeding)

SN - 978-1-4577-1399-6

T3 - Computer-Aided Design (ICCAD)

SP - 310

EP - 317

BT - 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -

Modeling the Computational Efficiency of 2-D and 3-D Silicon Processors for Early Chip Planning

Abstract

Publication series

Bibliographical note

UN SDGs

Research Groups and Themes

Keywords

Access to Document

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Cite this