Modelling and simulation of off-chip communication architectures for high-speed packet processors

J Engel, D Lacks, T Kocak

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Translated title of the contribution	Modelling and simulation of off-chip communication architectures for high-speed packet processors
Original language	English
Title of host publication	Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005
Publisher	ACTA Press
Pages	169 - 174
Number of pages	5
ISBN (Print)	0889865094
Publication status	Published - 24 Oct 2005

Conference Organiser: IASTED

Handle.net

@inproceedings{b84b65d9993d4a8ea86bbbbca451bfa5,

title = "Modelling and simulation of off-chip communication architectures for high-speed packet processors",

author = "J Engel and D Lacks and T Kocak",

note = "Conference Organiser: IASTED",

year = "2005",

month = oct,

day = "24",

language = "English",

isbn = "0889865094",

pages = "169 -- 174",

booktitle = "Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005",

publisher = "ACTA Press",

address = "Canada",

}

TY - GEN

T1 - Modelling and simulation of off-chip communication architectures for high-speed packet processors

AU - Engel, J

AU - Lacks, D

AU - Kocak, T

N1 - Conference Organiser: IASTED

PY - 2005/10/24

Y1 - 2005/10/24

M3 - Conference Contribution (Conference Proceeding)

SN - 0889865094

SP - 169

EP - 174

BT - Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005

PB - ACTA Press

ER -