Modelling and simulation of off-chip communication architectures for high-speed packet processors

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3 Citations (Scopus)

Translated title of the contribution	Modelling and simulation of off-chip communication architectures for high-speed packet processors
Original language	English
Pages (from-to)	1701 - 1714
Number of pages	14
Journal	Journal of Systems and Software
Volume	79 (12)
DOIs	https://doi.org/10.1016/j.jss.2006.01.033
Publication status	Published - Dec 2006

Publisher: Elsevier

Access to Document

@article{94ac723a881b443580ba85d0572557e1,

title = "Modelling and simulation of off-chip communication architectures for high-speed packet processors",

author = "J Engel and D Lacks and T Kocak",

note = "Publisher: Elsevier",

year = "2006",

month = dec,

doi = "10.1016/j.jss.2006.01.033",

language = "English",

volume = "79 (12)",

pages = "1701 -- 1714",

journal = "Journal of Systems and Software",

publisher = "Elsevier Inc.",

}

TY - JOUR

T1 - Modelling and simulation of off-chip communication architectures for high-speed packet processors

AU - Engel, J

AU - Lacks, D

AU - Kocak, T

N1 - Publisher: Elsevier

PY - 2006/12

Y1 - 2006/12

U2 - 10.1016/j.jss.2006.01.033

DO - 10.1016/j.jss.2006.01.033

M3 - Article (Academic Journal)

VL - 79 (12)

SP - 1701

EP - 1714

JO - Journal of Systems and Software

JF - Journal of Systems and Software

ER -