Multi-cell soft errors at the 16-nm FinFET technology node

N. Tam, B. L. Bhuva, L. W. Massengill, D. Ball, M. McCurdy, M. L. Alles, I. Chatterjee

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

13 Citations (Scopus)
502 Downloads (Pure)


Soft error performance of 16-nm FinFET SRAM designs fabricated using a commercial bulk CMOS process is evaluated using heavy-ions. Results included supply voltage variations show that multi-cell upsets dominate soft-error rates. Dual-port SRAM has higher cross-section than single-port SRAM but did not have any multi-cell upset across the bit-line direction. TCAD simulations showing the extent of the perturbation in the electric parameters as a function of particle LET support the experimental data.

Original languageEnglish
Title of host publicationIEEE International Reliability Physics Symposium Proceedings
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
ISBN (Print)9781467373623
Publication statusPublished - 26 May 2015
EventIEEE International Reliability Physics Symposium, IRPS 2015 - Monterey, United States
Duration: 19 Apr 201523 Apr 2015

Publication series

NameInternational Reliability Physics Symposium
ISSN (Print)1541-7026


ConferenceIEEE International Reliability Physics Symposium, IRPS 2015
Country/TerritoryUnited States


  • FinFET technology
  • multi-bit upsets
  • scaling
  • soft errors
  • SRAM
  • TCAD modeling


Dive into the research topics of 'Multi-cell soft errors at the 16-nm FinFET technology node'. Together they form a unique fingerprint.

Cite this