Nanocore/CMOS hybrid system-on-package (SoP) architecture for autonomous error-tolerant (AET) cellular array network

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

3 Citations (Scopus)

Original language	Undefined/Unknown
Title of host publication	5th IEEE Conference on Nanotechnology, 2005.
Pages	183-186 vol. 1
DOIs	https://doi.org/10.1109/NANO.2005.1500724
Publication status	Published - 2005

Research Groups and Themes

@inproceedings{19317f66696e4152ba543c644a69a265,

title = "Nanocore/CMOS hybrid system-on-package (SoP) architecture for autonomous error-tolerant (AET) cellular array network",

author = "R. Weerasekera and H. Tenhunen",

year = "2005",

doi = "10.1109/NANO.2005.1500724",

language = "Undefined/Unknown",

pages = "183--186 vol. 1",

booktitle = "5th IEEE Conference on Nanotechnology, 2005.",

}

TY - GEN

T1 - Nanocore/CMOS hybrid system-on-package (SoP) architecture for autonomous error-tolerant (AET) cellular array network

AU - Weerasekera, R.

AU - Tenhunen, H.

PY - 2005

Y1 - 2005

U2 - 10.1109/NANO.2005.1500724

DO - 10.1109/NANO.2005.1500724

M3 - Conference Contribution (Conference Proceeding)

SP - 183-186 vol. 1

BT - 5th IEEE Conference on Nanotechnology, 2005.

ER -