TY - GEN
T1 - Nanoelectromechanical Binary Comparator for Edge-Computing Applications
AU - Marot, Victor G R
AU - Bala Krishnan, Manu
AU - Kulsreshath, Mukesh Kumar
AU - Worsey, Elliott
AU - Weerasekera, Roshan
AU - Pamunuwa, I D B
N1 - Publisher Copyright:
© 2025 EDAA.
PY - 2025/5/21
Y1 - 2025/5/21
N2 - Bitwise comparison is a fundamental operation in many digital arithmetic functions and is ubiquitous in both datapath and control elements; for example, many machine learning algorithms depend on binary comparison. This work proposes a new class of binary comparator circuit using 4-terminal nanoelectromechanical (NEM) relays that use just 6 devices compared to 9 transistors in CMOS implementations. Moreover, NEM implementations are capable of withstanding much higher temperatures, up to 300°C, and radiation levels, well over 1 Mrad absorbed dose, conditions which are common across many industrial edge applications, with near zero standby power. A 1-bit magnitude and equality comparators comprising two in-plane silicon 4-terminal relays each were fabricated on a silicon-on-insulator substrate and electrically characterized for proof of concept, the first such demonstration. Using the 1-bit comparators as building blocks, a scalable tree-based topology is proposed to implement higher-order comparators, resulting in ≈47% reduction in device count over a CMOS implementation for a 64-bit comparator. Circuit level simulations of the comparators using accurate device models show that a single operation consumes at most 21 fJ a 9-fold reduction over the best CMOS offering in an equivalent process node.
AB - Bitwise comparison is a fundamental operation in many digital arithmetic functions and is ubiquitous in both datapath and control elements; for example, many machine learning algorithms depend on binary comparison. This work proposes a new class of binary comparator circuit using 4-terminal nanoelectromechanical (NEM) relays that use just 6 devices compared to 9 transistors in CMOS implementations. Moreover, NEM implementations are capable of withstanding much higher temperatures, up to 300°C, and radiation levels, well over 1 Mrad absorbed dose, conditions which are common across many industrial edge applications, with near zero standby power. A 1-bit magnitude and equality comparators comprising two in-plane silicon 4-terminal relays each were fabricated on a silicon-on-insulator substrate and electrically characterized for proof of concept, the first such demonstration. Using the 1-bit comparators as building blocks, a scalable tree-based topology is proposed to implement higher-order comparators, resulting in ≈47% reduction in device count over a CMOS implementation for a 64-bit comparator. Circuit level simulations of the comparators using accurate device models show that a single operation consumes at most 21 fJ a 9-fold reduction over the best CMOS offering in an equivalent process node.
UR - https://www.date-conference.com/
U2 - 10.23919/DATE64628.2025.10992913
DO - 10.23919/DATE64628.2025.10992913
M3 - Conference Contribution (Conference Proceeding)
SN - 9798331534646
T3 - Proceedings - Design, Automation, and Test in Europe Conference and Exhibition
BT - 2025 Design, Automation & Test in Europe Conference (DATE)
PB - Institute of Electrical and Electronics Engineers (IEEE)
T2 - Design, Automation and Test in Europe 2025 (DATE25)
Y2 - 31 March 2025 through 2 April 2025
ER -