We report a novel noise analysis for the leakage current during time-dependent dielectric degradation under bias stress, illustrated using AlGaN/GaN superlattice castellated field-effect transistors (SLCFETs). Gate step stress is a standard approach to test the robustness of the gate dielectric in off-state conditions. Here, by removing the background step transients measured using a standard parameter analyzer, the algorithm gives a quantitative value for the nonstationary superimposed noise in the dielectric leakage current during the test. Extraction of the power spectrum using windowing and a direct fit to the noise statistical distribution gives the noise magnitude. Although the technique allows the monitoring of noise increase during stress, it is shown that this is insufficient to clearly identify irreversible degradation in these devices. An additional low bias noise test between each step-stress bias has been used to detect the onset of permanent localized breakdown. This is manifested as both a change in noise magnitude and frequency dependence, occurring before it can be seen in leakage current or direct noise measurements.
Bibliographical notePublisher Copyright:
- Logic gates
- Noise measurement
- Semiconductor device measurement
- Transient analysis