Abstract
In deep sub-micron technologies, as the wires are placed ever closer and signal rise and fall times go into the sub-nano second region, increased crosstalk has implications on the data throughput and on signal integrity. Depending on the data correlation on the coupled lines, the delay can either decrease or increase. Here we show that in uniform coupled lines, the response for several important switching configurations has a dominant pole characteristic. This allows easy prediction for the average, worst-case and best-case delay of buffered lines. We show that the repeater numbering and sizing can be optimised to deal with crosstalk under different constraints to best match the application. Area and power issues are considered and all equations are checked against a dynamic circuit simulator (SPECTRE).
| Original language | Undefined/Unknown |
|---|---|
| Title of host publication | Proc. IEEE International Symposium on Circuits and Systems, (ISCAS) |
| Pages | I-97 |
| Volume | 1 |
| DOIs | |
| Publication status | Published - 1 May 2002 |
Research Groups and Themes
- Photonics and Quantum
Keywords
- VLSI
- circuit simulation
- crosstalk
- delays
- integrated circuit design
- integrated circuit interconnections
- integrated circuit modelling
- poles and zeros
- repeaters
- SPECTRE
- average delay
- best-case delay
- buffered lines
- data correlation
- data throughput
- deep sub-micron technologies
- dominant pole characteristic
- dynamic circuit simulator
- dynamic delay
- repeater insertion
- signal fall times
- signal integrity
- signal rise times
- switching configurations
- uniform coupled lines
- worst-case delay
- Capacitance
- Constraint optimization
- Delay effects
- Delay lines
- Equations
- Repeaters
- Switches
- Throughput
- Very large scale integration
- Wires