Abstract
This paper discusses signal integrity (SI) issues and signalling techniques for Through Silicon Via (TSV) interconnects in 3-D Integrated Circuits (ICs). Field-solver extracted parasitics of TSVs have been employed in Spice simulations to investigate the effect of each parasitic component on performance metrics such as delay and crosstalk and identify a reduced-order electrical model that captures all relevant effects. We show that in dense TSV structures voltage-mode (VM) signalling does not lend itself to achieving high data-rates, and that current-mode (CM) signalling is more effective for high throughput signalling as well as jitter reduction. Data rates, energy consumption and coupled noise for the different signalling modes are extracted.
| Original language | Undefined/Unknown |
|---|---|
| Title of host publication | 2010 Design, Automation Test in Europe Conference Exhibition (DATE 2010) |
| Pages | 1325-1328 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 1 Mar 2010 |
Research Groups and Themes
- Photonics and Quantum
Keywords
- SPICE
- crosstalk
- integrated circuit interconnections
- 3D integrated circuits
- Spice simulations
- current-mode signalling
- jitter reduction
- reduced-order electrical model
- signal integrity
- through-silicon via interconnects
- voltage-mode signalling
- Circuit simulation
- Crosstalk
- Delay effects
- Integrated circuit interconnections
- Measurement
- Silicon
- Three-dimensional integrated circuits
- Through-silicon vias
- Virtual manufacturing
- Voltage
