On the design of two single event tolerant slave latches for scan delay testing

Yang Lu; Fabrizio Lombardi; Salvatore Pontarelli; Marco Ottavi

doi:10.1109/DFT.2012.6378202

On the design of two single event tolerant slave latches for scan delay testing

Yang Lu^*, Fabrizio Lombardi, Salvatore Pontarelli, Marco Ottavi

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

2 Citations (Scopus)

Abstract

This paper proposes two new slave latches for improving the Single Event Upset (SEU) tolerance of a flipflop in scan delay testing. The two proposed slave latches utilize additional circuitry to increase the critical charge of the flip-flop compared to designs found in the technical literature. The first (second) latch design achieves a 5.6 (2.4) times larger critical charge with 11% (4%) delay and 16 % (9%) power consumption overhead at 32nm feature size as compared to the best design found in the technical literature. Moreover, it is shown that the proposed slave latches have also superior performance in the presence of a single event with a multiple node upset.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Pages	67-72
Number of pages	6
DOIs	https://doi.org/10.1109/DFT.2012.6378202
Publication status	Published - 1 Dec 2012
Event	2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012 - Austin, TX, United Kingdom Duration: 3 Oct 2012 → 5 Oct 2012

Conference

Conference	2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012
Country/Territory	United Kingdom
City	Austin, TX
Period	3/10/12 → 5/10/12

Keywords

flip-flop
Radiation hardening
Single Event Upset
soft error

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title = "On the design of two single event tolerant slave latches for scan delay testing",

abstract = "This paper proposes two new slave latches for improving the Single Event Upset (SEU) tolerance of a flipflop in scan delay testing. The two proposed slave latches utilize additional circuitry to increase the critical charge of the flip-flop compared to designs found in the technical literature. The first (second) latch design achieves a 5.6 (2.4) times larger critical charge with 11% (4%) delay and 16 % (9%) power consumption overhead at 32nm feature size as compared to the best design found in the technical literature. Moreover, it is shown that the proposed slave latches have also superior performance in the presence of a single event with a multiple node upset.",

keywords = "flip-flop, Radiation hardening, Single Event Upset, soft error",

author = "Yang Lu and Fabrizio Lombardi and Salvatore Pontarelli and Marco Ottavi",

year = "2012",

month = dec,

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doi = "10.1109/DFT.2012.6378202",

language = "English",

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booktitle = "Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",

note = "2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012 ; Conference date: 03-10-2012 Through 05-10-2012",

}

Lu, Y, Lombardi, F, Pontarelli, S & Ottavi, M 2012, On the design of two single event tolerant slave latches for scan delay testing. in Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems., 6378202, pp. 67-72, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, United Kingdom, 3/10/12. https://doi.org/10.1109/DFT.2012.6378202

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T1 - On the design of two single event tolerant slave latches for scan delay testing

AU - Lu, Yang

AU - Lombardi, Fabrizio

AU - Pontarelli, Salvatore

AU - Ottavi, Marco

PY - 2012/12/1

Y1 - 2012/12/1

N2 - This paper proposes two new slave latches for improving the Single Event Upset (SEU) tolerance of a flipflop in scan delay testing. The two proposed slave latches utilize additional circuitry to increase the critical charge of the flip-flop compared to designs found in the technical literature. The first (second) latch design achieves a 5.6 (2.4) times larger critical charge with 11% (4%) delay and 16 % (9%) power consumption overhead at 32nm feature size as compared to the best design found in the technical literature. Moreover, it is shown that the proposed slave latches have also superior performance in the presence of a single event with a multiple node upset.

AB - This paper proposes two new slave latches for improving the Single Event Upset (SEU) tolerance of a flipflop in scan delay testing. The two proposed slave latches utilize additional circuitry to increase the critical charge of the flip-flop compared to designs found in the technical literature. The first (second) latch design achieves a 5.6 (2.4) times larger critical charge with 11% (4%) delay and 16 % (9%) power consumption overhead at 32nm feature size as compared to the best design found in the technical literature. Moreover, it is shown that the proposed slave latches have also superior performance in the presence of a single event with a multiple node upset.

KW - flip-flop

KW - Radiation hardening

KW - Single Event Upset

KW - soft error

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DO - 10.1109/DFT.2012.6378202

M3 - Conference Contribution (Conference Proceeding)

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SN - 9781467330428

SP - 67

EP - 72

BT - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

T2 - 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012

Y2 - 3 October 2012 through 5 October 2012

ER -

On the design of two single event tolerant slave latches for scan delay testing

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