On the design of two single event tolerant slave latches for scan delay testing

Yang Lu*, Fabrizio Lombardi, Salvatore Pontarelli, Marco Ottavi

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

2 Citations (Scopus)

Abstract

This paper proposes two new slave latches for improving the Single Event Upset (SEU) tolerance of a flipflop in scan delay testing. The two proposed slave latches utilize additional circuitry to increase the critical charge of the flip-flop compared to designs found in the technical literature. The first (second) latch design achieves a 5.6 (2.4) times larger critical charge with 11% (4%) delay and 16 % (9%) power consumption overhead at 32nm feature size as compared to the best design found in the technical literature. Moreover, it is shown that the proposed slave latches have also superior performance in the presence of a single event with a multiple node upset.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Pages67-72
Number of pages6
DOIs
Publication statusPublished - 1 Dec 2012
Event2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012 - Austin, TX, United Kingdom
Duration: 3 Oct 20125 Oct 2012

Conference

Conference2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012
CountryUnited Kingdom
CityAustin, TX
Period3/10/125/10/12

Keywords

  • flip-flop
  • Radiation hardening
  • Single Event Upset
  • soft error

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