On the Hardware Reduction of z-Datapath of Vectoring CORDIC

R. Staphenhurst, Koushik Maharatna, Jimson Mathew, J. Nunez-Yanez, Pradhan Dhiraj

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

5 Citations (Scopus)

Abstract

— In this article we present a novel design of a hardware optimal vectoring CORDIC processor. We present a mathematical theory to show that using bipolar binary notation it is possible to eliminate all the arithmetic computations required along the z-datapath. Using this technique it is possible to achieve three and 1.5 times reduction in the number of registers and adder respectively compared to conventional CORDIC. Following this, a 16-bit vectoring CORDIC is designed for the application in Synchronizer for IEEE 802.11a standard. The total area and dynamic power consumption of the processor is 0.14 mm2 and 700μW respectively when synthesized in 0.18μm CMOS library which shows its effectiveness as a low-area low-power processor.
Translated title of the contributionOn the Hardware Reduction of z-Datapath of Vectoring CORDIC
Original languageEnglish
Title of host publicationIEEE International Conference on Circuits and Systems, (ISCAS 2007), USA
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Publication statusPublished - 2007

Bibliographical note

Other page information: -
Conference Proceedings/Title of Journal: IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA
Other identifier: 2000663

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