On the Hardware Reduction of z-Datapath of Vectoring CORDIC

R. Staphenhurst; Koushik Maharatna; Jimson Mathew; J. Nunez-Yanez; Pradhan Dhiraj

On the Hardware Reduction of z-Datapath of Vectoring CORDIC

R. Staphenhurst, Koushik Maharatna, Jimson Mathew, J. Nunez-Yanez, Pradhan Dhiraj

Department of Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

5 Citations (Scopus)

Abstract

— In this article we present a novel design of a hardware optimal vectoring CORDIC processor. We present a mathematical theory to show that using bipolar binary notation it is possible to eliminate all the arithmetic computations required along the z-datapath. Using this technique it is possible to achieve three and 1.5 times reduction in the number of registers and adder respectively compared to conventional CORDIC. Following this, a 16-bit vectoring CORDIC is designed for the application in Synchronizer for IEEE 802.11a standard. The total area and dynamic power consumption of the processor is 0.14 mm2 and 700μW respectively when synthesized in 0.18μm CMOS library which shows its effectiveness as a low-area low-power processor.

Translated title of the contribution	On the Hardware Reduction of z-Datapath of Vectoring CORDIC
Original language	English
Title of host publication	IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Publication status	Published - 2007

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Conference Proceedings/Title of Journal: IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA
Other identifier: 2000663

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@inproceedings{2997042c59424952a89b98aee14015f2,

title = "On the Hardware Reduction of z-Datapath of Vectoring CORDIC",

abstract = "— In this article we present a novel design of a hardware optimal vectoring CORDIC processor. We present a mathematical theory to show that using bipolar binary notation it is possible to eliminate all the arithmetic computations required along the z-datapath. Using this technique it is possible to achieve three and 1.5 times reduction in the number of registers and adder respectively compared to conventional CORDIC. Following this, a 16-bit vectoring CORDIC is designed for the application in Synchronizer for IEEE 802.11a standard. The total area and dynamic power consumption of the processor is 0.14 mm2 and 700μW respectively when synthesized in 0.18μm CMOS library which shows its effectiveness as a low-area low-power processor. ",

author = "R. Staphenhurst and Koushik Maharatna and Jimson Mathew and J. Nunez-Yanez and Pradhan Dhiraj",

note = "Other page information: - Conference Proceedings/Title of Journal: IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA Other identifier: 2000663",

year = "2007",

language = "English",

booktitle = "IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

}

On the Hardware Reduction of z-Datapath of Vectoring CORDIC. / Staphenhurst, R.; Maharatna, Koushik; Mathew, Jimson et al.
IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA. Institute of Electrical and Electronics Engineers (IEEE), 2007.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - On the Hardware Reduction of z-Datapath of Vectoring CORDIC

AU - Staphenhurst, R.

AU - Maharatna, Koushik

AU - Mathew, Jimson

AU - Nunez-Yanez, J.

AU - Dhiraj, Pradhan

N1 - Other page information: - Conference Proceedings/Title of Journal: IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA Other identifier: 2000663

PY - 2007

Y1 - 2007

N2 - — In this article we present a novel design of a hardware optimal vectoring CORDIC processor. We present a mathematical theory to show that using bipolar binary notation it is possible to eliminate all the arithmetic computations required along the z-datapath. Using this technique it is possible to achieve three and 1.5 times reduction in the number of registers and adder respectively compared to conventional CORDIC. Following this, a 16-bit vectoring CORDIC is designed for the application in Synchronizer for IEEE 802.11a standard. The total area and dynamic power consumption of the processor is 0.14 mm2 and 700μW respectively when synthesized in 0.18μm CMOS library which shows its effectiveness as a low-area low-power processor.

AB - — In this article we present a novel design of a hardware optimal vectoring CORDIC processor. We present a mathematical theory to show that using bipolar binary notation it is possible to eliminate all the arithmetic computations required along the z-datapath. Using this technique it is possible to achieve three and 1.5 times reduction in the number of registers and adder respectively compared to conventional CORDIC. Following this, a 16-bit vectoring CORDIC is designed for the application in Synchronizer for IEEE 802.11a standard. The total area and dynamic power consumption of the processor is 0.14 mm2 and 700μW respectively when synthesized in 0.18μm CMOS library which shows its effectiveness as a low-area low-power processor.

M3 - Conference Contribution (Conference Proceeding)

BT - IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -

On the Hardware Reduction of z-Datapath of Vectoring CORDIC

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