On the mitigation of cache hostile memory access patterns on many-core CPU architectures

Tom Deakin*, Wayne Gaudin, Simon McIntosh-Smith

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

5 Citations (Scopus)
245 Downloads (Pure)

Abstract

Kernels with low arithmetic intensity with memory footprint exceeding cache sizes are typically categorised as memory bandwidth bound. Kernels of this class are typically limited by hardware memory bandwidth. In this work we contribute a simple memory access pattern, derived from a widely-used upwinded stencil-style benchmark, which presents significant challenges for cache-based architectures. The problem appears to grow worse as CPU core counts increase, and the pattern in its initial form shows no benefit from the new high-bandwidth memory now appearing on the Intel Xeon Phi (Knights Landing) family of processors. We describe the memory access scenarios which appear to be causing lower than expected cache performance, before presenting optimisations to mitigate the problem. These optimisations result in useful effective memory bandwidth and runtime improvements by up to 4X on cache based architectures. Results are presented on the Intel Xeon (Broadwell) and Xeon Phi (Knights Landing) processors.

Original languageEnglish
Title of host publicationHigh Performance Computing - ISC High Performance 2017 International Workshops, DRBSD, ExaComm, HCPM, HPC-IODC, IWOPH, IXPUG, P^3MA, VHPC, Visualization at Scale, WOPSSS, Revised Selected Papers
PublisherSpringer
Pages348-362
Number of pages15
ISBN (Electronic)9783319586670
ISBN (Print)9783319676296
DOIs
Publication statusPublished - 2017
Event32nd International Conference on High Performance Computing, ISC High Performance 2017 - Frankfurt, Germany
Duration: 18 Jun 201722 Jun 2017

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume10524 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference32nd International Conference on High Performance Computing, ISC High Performance 2017
CountryGermany
CityFrankfurt
Period18/06/1722/06/17

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