Optical buffering for chip multiprocessors: A 16GHz optical cache memory architecture

Computer Science

• Physical Layer 100%
• Memory Architecture 100%
• Cache Memory 100%
• Chip Multiprocessor 100%
• Capacity Requirement 50%
• Speed-up 50%
• Building-Blocks 50%
• Total Capacity 50%
• Write Operation 50%
• Memory Address 50%
• L2 Cache 50%
• Read Operation 50%
• L1 Cache 50%
• Associativity 50%
• Direct Mapping 50%