Optical RAM-enabled cache memory and optical routing for chip multiprocessors: Technologies and architectures

Nikos Pleros, Pavlos Maniotis, Theonitsa Alexoudi, Dimitris Fitsios, Christos Vagionas, Sotiris Papaioannou, K. Vyrsokinos, George T. Kanellos

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

1 Citation (Scopus)

Abstract

The processor-memory performance gap, commonly referred to as “Memory Wall†problem, owes to the speed mismatch between processor and electronic RAM clock frequencies, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In this article, we present our recent work spanning from Si-based integrated optical RAM cell architectures up to complete optical cache memory architectures for Chip Multiprocessor configurations. Moreover, we discuss on e/o router subsystems with up to Tb/s routing capacity for cache interconnection purposes within CMP configurations, currently pursued within the FP7 PhoxTrot project.

Original languageEnglish
Title of host publicationOptical Interconnects XIV
PublisherSociety of Photo-Optical Instrumentation Engineers (SPIE)
Volume8991
ISBN (Print)9780819499042
DOIs
Publication statusPublished - 1 Jan 2014
EventOptical Interconnects XIV - San Francisco, CA, United States
Duration: 3 Feb 20145 Feb 2014

Conference

ConferenceOptical Interconnects XIV
CountryUnited States
CitySan Francisco, CA
Period3/02/145/02/14

Keywords

  • Optical interconnects
  • Optical memory
  • Optical RAM
  • Optical routing
  • Silicon photonics

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    Pleros, N., Maniotis, P., Alexoudi, T., Fitsios, D., Vagionas, C., Papaioannou, S., Vyrsokinos, K., & Kanellos, G. T. (2014). Optical RAM-enabled cache memory and optical routing for chip multiprocessors: Technologies and architectures. In Optical Interconnects XIV (Vol. 8991). [89910Z] Society of Photo-Optical Instrumentation Engineers (SPIE). https://doi.org/10.1117/12.2042732