Optical RAM-enabled cache memory and optical routing for chip multiprocessors: Technologies and architectures

Nikos Pleros; Pavlos Maniotis; Theonitsa Alexoudi; Dimitris Fitsios; Christos Vagionas; Sotiris Papaioannou; K. Vyrsokinos; George T. Kanellos

doi:10.1117/12.2042732

Optical RAM-enabled cache memory and optical routing for chip multiprocessors: Technologies and architectures

Nikos Pleros, Pavlos Maniotis, Theonitsa Alexoudi, Dimitris Fitsios, Christos Vagionas, Sotiris Papaioannou, K. Vyrsokinos, George T. Kanellos

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

2 Citations (Scopus)

Abstract

The processor-memory performance gap, commonly referred to as â€œMemory Wallâ€ problem, owes to the speed mismatch between processor and electronic RAM clock frequencies, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In this article, we present our recent work spanning from Si-based integrated optical RAM cell architectures up to complete optical cache memory architectures for Chip Multiprocessor configurations. Moreover, we discuss on e/o router subsystems with up to Tb/s routing capacity for cache interconnection purposes within CMP configurations, currently pursued within the FP7 PhoxTrot project.

Original language	English
Title of host publication	Optical Interconnects XIV
Publisher	Society of Photo-Optical Instrumentation Engineers (SPIE)
Volume	8991
ISBN (Print)	9780819499042
DOIs	https://doi.org/10.1117/12.2042732
Publication status	Published - 1 Jan 2014
Event	Optical Interconnects XIV - San Francisco, CA, United States Duration: 3 Feb 2014 → 5 Feb 2014

Conference

Conference	Optical Interconnects XIV
Country/Territory	United States
City	San Francisco, CA
Period	3/02/14 → 5/02/14

Keywords

Optical interconnects
Optical memory
Optical RAM
Optical routing
Silicon photonics

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Pleros, N., Maniotis, P., Alexoudi, T., Fitsios, D., Vagionas, C., Papaioannou, S., Vyrsokinos, K., & Kanellos, G. T. (2014). Optical RAM-enabled cache memory and optical routing for chip multiprocessors: Technologies and architectures. In Optical Interconnects XIV (Vol. 8991). Article 89910Z Society of Photo-Optical Instrumentation Engineers (SPIE). https://doi.org/10.1117/12.2042732

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Pleros, N, Maniotis, P, Alexoudi, T, Fitsios, D, Vagionas, C, Papaioannou, S, Vyrsokinos, K & Kanellos, GT 2014, Optical RAM-enabled cache memory and optical routing for chip multiprocessors: Technologies and architectures. in Optical Interconnects XIV. vol. 8991, 89910Z, Society of Photo-Optical Instrumentation Engineers (SPIE), Optical Interconnects XIV, San Francisco, CA, United States, 3/02/14. https://doi.org/10.1117/12.2042732

Optical RAM-enabled cache memory and optical routing for chip multiprocessors: Technologies and architectures. / Pleros, Nikos; Maniotis, Pavlos; Alexoudi, Theonitsa et al.
Optical Interconnects XIV. Vol. 8991 Society of Photo-Optical Instrumentation Engineers (SPIE), 2014. 89910Z.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

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AU - Vagionas, Christos

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AU - Vyrsokinos, K.

AU - Kanellos, George T.

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Optical RAM-enabled cache memory and optical routing for chip multiprocessors: Technologies and architectures

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