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Optics in Computing: from photonic Network-on-Chip to Chip-to-Chip Interconnects and Disintegrated Architectures

Research output: Contribution to journalArticle

  • Theonitsa Alexoudi
  • Nikolaos Terzenidis
  • Stelios Pitris
  • Miltiadis Moralis-Pegios
  • Pavlos Maniotis
  • Christos Vagionas
  • Charoula Mitsolidou
  • George Mourgias-Alexandris
  • George T. Kanellos
  • Amalia Miliou
  • Konstantinos Vyrsokinos
  • Nikos Pleros
Original languageEnglish
Number of pages17
JournalJournal of Lightwave Technology
Early online date15 Oct 2018
DateAccepted/In press - 8 Oct 2018
DateE-pub ahead of print (current) - 15 Oct 2018


Following a decade of radical advances in the areas of integrated photonics and computing architectures, we discuss the use of optics in the current computing landscape attempting to re-define and refine their role based on the progress in both research fields. We present the current set of critical challenges faced by the computing industry and provide a thorough review of photonic Network-on-Chip (pNoC) architectures and experimental demonstrations, concluding to the main obstacles that still impede the materialization of these concepts. We propose the employment of optics in chip-to-chip (C2C) computing architectures rather than on-chip layouts towards reaping their benefits while avoiding technology limitations on the way to manycore set-ups. We identify multisocket boards as the most prominent application area and present recent advances in optically enabled multisocket boards, revealing successful 40Gb/s transceiver and routing capabilities via integrated photonics. These results indicate the strong potential to bring energy consumption down by more than 60% compared to current QuickPath Interconnect (QPI) protocol, while turning multisocket architectures into a single-hop low-latency setup for even more than 4 interconnected sockets, which form currently the electronic baseline. We go one step further and demonstrate how optically-enabled 8-socket boards can be combined via a 256x256 Hipo-aos Optical Packet Switch into a powerful 256-node disaggregated system with less than 335nsec latency, forming a highly promising solution for the latency-critical rack-scale memory disaggregation era. Finally, we discuss the perspective for disintegrated computing via optical technologies as a means to increase the number of synergized high-performance cores overcoming die area constraints, introducing also the concept of cache disintegration via the use of future off-die ultra-fast optical cache memory chiplets.

    Research areas

  • Computer architecture, computing architectures, disintegrated computing, macrochip, multisocket boards, Network-on-Chip, Optical interconnections, optical memory, optical packet switch, Optical packet switching, Optics, Photonics, rack-scale disaggregation, Silicon, silicon photonics, System-on-chip

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    Rights statement: This is the author accepted manuscript (AAM). The final published version (version of record) is available online via IEEE at . Please refer to any applicable terms of use of the publisher.

    Accepted author manuscript, 1 MB, PDF document


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