Optimal Signaling Techniques for Through Silicon Vias in 3-D Integrated Circuit Packages

Matt Grange, Roshan Weerasekera, Dinesh Pamunuwa

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Abstract

We investigate optimal techniques for signaling over Through Silicon Vias (TSV) in 3-D circuits to derive design guidelines for maximizing data rate, energy and signal integrity. Low-voltage differential (LVDS) and low-voltage single-ended (LVSE), voltage mode (VM) and current mode (CM) drivers and receivers are implemented in a 65 nm CMOS technology and SPICE simulations with accurate TSV electrical models including coupling effects extracted from a commercial field solver. Trade-offs between the signaling circuits are discussed and the results quantified in terms of data rate, delay variation, noise amplitude and energy consumption.
Original languageUndefined/Unknown
Title of host publicationProc. IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)
Pages237-240
Number of pages4
DOIs
Publication statusPublished - 1 Oct 2010

Keywords

  • CMOS integrated circuits
  • SPICE
  • driver circuits
  • integrated circuit modelling
  • integrated circuit packaging
  • low-power electronics
  • three-dimensional integrated circuits
  • 3D integrated circuit packages
  • CMOS technology
  • SPICE simulations
  • coupling effects
  • current mode driver
  • energy integrity
  • low-voltage differential driver
  • low-voltage single-ended driver
  • optimal signaling
  • signal integrity
  • signaling circuits
  • size 65 nm
  • through silicon vias
  • voltage mode driver
  • Delay
  • Driver circuits
  • Integrated circuit modeling
  • Inverters
  • Noise
  • Receivers
  • Through-silicon vias

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