Optimising Bandwidth over Deep Sub-Micron Interconnect

Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

3 Citations (Scopus)

Abstract

In deep sub-micron (DSM) circuits proper analysis of interconnect delay is very important. When relatively long wires are placed in parallel, it is essential to include the effects of cross-talk on delay. In a parallel wire structure, the exact spacing and size of the wires determine both the resistance and the distribution of the capacitance between the ground plane and the adjacent signal carrying conductors, and have a direct effect on the delay. Repeater insertion depending on whether it is optimal or constrained, affects the delay in different ways. Considering all these effects we show that there is a clear optimum configuration for the wires which maximises the total bandwidth. Our analysis is valid for lossy interconnects as are typical of wires in DSM technologies.
Original languageUndefined/Unknown
Title of host publicationProc. IEEE International Symposium on Circuits and Systems, (ISCAS)
PagesIV-193
Volume4
DOIs
Publication statusPublished - 1 May 2002

Keywords

  • VLSI
  • capacitance
  • crosstalk
  • delay estimation
  • distributed parameter networks
  • integrated circuit interconnections
  • integrated circuit modelling
  • bandwidth optimisation
  • capacitance distribution
  • cross-talk effects
  • deep sub-micron circuits
  • interconnect delay
  • lossy interconnects
  • optimum wire configuration
  • parallel wire structure
  • repeater insertion
  • signal carrying conductors
  • total bandwidth maximisation
  • Bandwidth
  • Capacitance
  • Delay effects
  • Delay lines
  • Equations
  • Frequency
  • Integrated circuit interconnections
  • Repeaters
  • Switches
  • Wires

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