Optimized implementation of RNS FIR filters based on FPGAs

Salvatore Pontarelli*, Gian Carlo Cardarilli, Marco Re, Adelio Salsano

*Corresponding author for this work

Research output: Contribution to journalArticle (Academic Journal)peer-review

12 Citations (Scopus)


In this paper optimized Residue Number System (RNS) arithmetic blocks to better exploit some of the architectural characteristics of the last generation FPGAs are presented. The implementation of modulo m adders, modulo m constant and general multipliers, input and output converters are presented. These architectures are based on moduli sets chosen in order to optimally use the 6-input Look-Up Tables (LUTs) available in the Complex Logic Blocks (CLBs) of the new generation FPGAs. Experiments based on the implementation of Finite Impulse Response (FIR) filters characterized by different number of taps and wordlengths shows that the use of RNS together with suitable moduli sets optimally fits the 6-input LUTs in the last generation FPGAs architectures.

Original languageEnglish
Pages (from-to)201-212
Number of pages12
JournalJournal of Signal Processing Systems
Issue number3
Publication statusPublished - 1 Jun 2012


  • FIR filters
  • FPGA
  • Residue Number System


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