P3 (Power-Performance-Process) Optimization of Nano-CMOS SRAM using Statistical DOE-ILP

Thakral G., Mohanty S. P., Dhiraj Pradhan

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

6 Citations (Scopus)
Original languageEnglish
Title of host publication11th IEEE International Symposium on Quality Electronic Design (ISQED)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Publication statusPublished - 2010

Bibliographical note

Other page information: -
Conference Proceedings/Title of Journal: 11th IEEE International Symposium on Quality Electronic Design (ISQED)
Other identifier: 2001148

Cite this

G., T., S. P., M., & Pradhan, D. (2010). P3 (Power-Performance-Process) Optimization of Nano-CMOS SRAM using Statistical DOE-ILP. In 11th IEEE International Symposium on Quality Electronic Design (ISQED) Institute of Electrical and Electronics Engineers (IEEE). http://www.cs.bris.ac.uk/Publications/pub_master.jsp?id=2001148