Parallel evaluation of a parallel architecture by means of calibrated emulation

HL Muller, PWA Stallard, DHD Warren, S Raina

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Translated title of the contribution	Parallel evaluation of a parallel architecture by means of calibrated emulation
Original language	English
Title of host publication	Parallel processing (1994 Apr : Cancun, Mexico)
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Number of pages	15
ISBN (Print)	0818656026
Publication status	Published - 1993

Other: CSTR-93-13

Handle.net

@inproceedings{9ac816a8fe0b4d2ba79bd500d0ecc3b4,

title = "Parallel evaluation of a parallel architecture by means of calibrated emulation",

author = "HL Muller and PWA Stallard and DHD Warren and S Raina",

note = "Other: CSTR-93-13",

year = "1993",

language = "English",

isbn = "0818656026",

booktitle = "Parallel processing (1994 Apr : Cancun, Mexico)",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

}

TY - GEN

T1 - Parallel evaluation of a parallel architecture by means of calibrated emulation

AU - Muller, HL

AU - Stallard, PWA

AU - Warren, DHD

AU - Raina, S

N1 - Other: CSTR-93-13

PY - 1993

Y1 - 1993

M3 - Conference Contribution (Conference Proceeding)

SN - 0818656026

BT - Parallel processing (1994 Apr : Cancun, Mexico)

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -