Parallel Evaluation of a Parallel Architecture by means of Calibrated Emulation

Henk L Muller, Paul W A Stallard, David H D Warren, Sanjay Raina

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

3 Citations (Scopus)

Translated title of the contribution	Parallel Evaluation of a Parallel Architecture by means of Calibrated Emulation
Original language	English
Title of host publication	Unknown
Publisher	IEEE Computer Society
Pages	260 - 267
Number of pages	7
ISBN (Print)	0818656026
Publication status	Published - 1994

Conference Proceedings/Title of Journal: Proceedings of the 8th International Parallel Processing Symposium

Access to Document

@inproceedings{aec20f20d0cc4b40ae69280129bc0ddb,

title = "Parallel Evaluation of a Parallel Architecture by means of Calibrated Emulation",

author = "Muller, \{Henk L\} and Stallard, \{Paul W A\} and Warren, \{David H D\} and Sanjay Raina",

note = "Conference Proceedings/Title of Journal: Proceedings of the 8th International Parallel Processing Symposium",

year = "1994",

language = "English",

isbn = "0818656026",

pages = "260 -- 267",

booktitle = "Unknown",

publisher = "IEEE Computer Society",

address = "United States",

}

TY - GEN

T1 - Parallel Evaluation of a Parallel Architecture by means of Calibrated Emulation

AU - Muller, Henk L

AU - Stallard, Paul W A

AU - Warren, David H D

AU - Raina, Sanjay

N1 - Conference Proceedings/Title of Journal: Proceedings of the 8th International Parallel Processing Symposium

PY - 1994

Y1 - 1994

M3 - Conference Contribution (Conference Proceeding)

SN - 0818656026

SP - 260

EP - 267

BT - Unknown

PB - IEEE Computer Society

ER -