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Parallel Multiprocessing and Scheduling on the Heterogeneous Xeon+FPGA Platform

Research output: Contribution to journalArticle

Original languageEnglish
Number of pages21
JournalJournal of Supercomputing
Early online date18 Jun 2019
DateAccepted/In press - 13 Jun 2019
DateE-pub ahead of print (current) - 18 Jun 2019


Heterogeneous computing that exploits simultaneous co-processing with different device types has been shown to be effective at both increasing performance and reducing energy consumption. In this paper we extend a scheduling framework encapsulated in a high level C++ template, and previously developed
for heterogeneous chips comprising CPU and GPU cores, to new high-performance platforms for the data center, which include a cache coherent FPGA fabric and many core CPU resources. Our goal is to evaluate the suitability of our framework with these new FPGA-based platforms, identifying performance benefits and limitations. We target the state-of-the-art HARP processor that includes 14 high-end Xeon-class tightly coupled to a FPGA device located in the same package. We select 8 benchmarks from the High Performance Computing domain that have been ported and optimized for this heterogeneous platform. The results show that
a dynamic and adaptive scheduler that exploits simultaneous processing among the devices can improve performance up to a factor of 8x compared to the best alternative solutions that only use the CPU cores or the FPGA fabric. Moreover, our proposal achieves up to 15% and 37% of improvement compared to the best
heterogeneous solutions found with a Dynamic and Static schedulers, respectively.

    Research areas

  • Adaptive chunk size, Hybrid algorithm, Heterogeneous scheduling, Parallel_for template, FPGA, Heterogeneous architecture



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    Embargo ends: 18/06/20

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