Abstract
An effective on chip scheme for correcting
double soft errors in the memory chip is presented. Any
random double errors correction in the memory cell can be
incorporated with minimum hardware. The area, delay and
power for additional error-correcting hardware into a
memory design have been presented. The on-chip error
correction technique for the specific memory architecture
results in considerable power savings and effective error
tolerance. It significantly enhances the reliability with low
area overhead.
| Translated title of the contribution | Performance Analysis of an Error Tolerant Low Power Memory Architecture |
|---|---|
| Original language | English |
| Title of host publication | IEEE International Design and Test Workshop |
| Publication status | Published - 2006 |
Bibliographical note
Other page information: -Conference Proceedings/Title of Journal: IEEE International Design and Test Workshop
Other identifier: 2000610