Translated title of the contribution | Petri net modelling of VHDL simulation cycle for high level synthesis purpose |
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Original language | English |
Title of host publication | Unknown |
Pages | 35 - 46 |
Volume | 5-8 |
Publication status | Published - 1996 |
Petri net modelling of VHDL simulation cycle for high level synthesis purpose
J Mirkowski, K Bilinski, EL Dagless
Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)