Petri net modelling of VHDL simulation cycle for high level synthesis  purpose

J Mirkowski, K Bilinski, EL Dagless

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Translated title of the contribution	Petri net modelling of VHDL simulation cycle for high level synthesis purpose
Original language	English
Title of host publication	Unknown
Pages	35 - 46
Volume	5-8
Publication status	Published - 1996

Conference Proceedings/Title of Journal: SIG-VHDL Spring'96 Conference VHDL user Forum Europe

Handle.net

@inproceedings{80c18d3908b6462fb837ba10c3f34210,

title = "Petri net modelling of VHDL simulation cycle for high level synthesis purpose",

author = "J Mirkowski and K Bilinski and EL Dagless",

note = "Conference Proceedings/Title of Journal: SIG-VHDL Spring'96 Conference VHDL user Forum Europe",

year = "1996",

language = "English",

isbn = "382654629",

volume = "5-8",

pages = "35 -- 46",

booktitle = "Unknown",

}

TY - GEN

T1 - Petri net modelling of VHDL simulation cycle for high level synthesis purpose

AU - Mirkowski, J

AU - Bilinski, K

AU - Dagless, EL

N1 - Conference Proceedings/Title of Journal: SIG-VHDL Spring'96 Conference VHDL user Forum Europe

PY - 1996

Y1 - 1996

M3 - Conference Contribution (Conference Proceeding)

SN - 382654629

VL - 5-8

SP - 35

EP - 46

BT - Unknown

ER -