Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh

Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa, Roshan Weerasekera, Zhonghai Lu, Axel Jantsch, Dave Shippen

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

1 Citation (Scopus)


The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The relatively low parasitics of TSVs compared to the on-chip 2-D interconnect allow for higher signaling speeds between chip layers. The system-level impact on overall network performance as a result of clocking vertical packets at a higher rate through the TSV interconnect is simulated and reported.
Original languageUndefined/Unknown
Title of host publicationProc. IEEE International Conference on 3D System Integration (3DIC)
Number of pages7
Publication statusPublished - 1 Sep 2009


  • integrated circuit interconnections
  • network analysis
  • network-on-chip
  • cycle-accurate RTL simulator
  • horizontal network link
  • multiclock 3-dimensional network-on-chip mesh architecture
  • on-chip interconnect
  • physical mapping
  • switches
  • system-level impact
  • through silicon vias
  • vertical network link
  • CMOS technology
  • Clocks
  • Communication switching
  • Delay
  • Integrated circuit interconnections
  • Network-on-a-chip
  • Silicon
  • Switches
  • Three-dimensional integrated circuits
  • Through-silicon vias

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