Pipelined DFE architectures using delayed coefficient adaptation

R Perry; DR Bull; AR Nix

doi:10.1109/82.700934

Pipelined DFE architectures using delayed coefficient adaptation

R Perry, DR Bull, AR Nix

Research output: Contribution to journal › Article (Academic Journal) › peer-review

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Abstract

In this paper the delayed least-mean-square (DLMS) algorithm is proposed for training a transversal filter-based decision feedback equalizer (DFE). Delays in the filter coefficient update process are used to pipeline the DFE, thereby increasing the throughput rate, for a given speed of hardware. The filter structures selected for the feedforward and feedback section of the DFE facilitate the use of a shared error signal, thereby reducing communication costs. The new resulting structure is highly modular and is very suitable for very large scale integration (VLSI) implementation. A pipelined form for the normalized least-mean-square algorithm (NMLS) is also obtained which removes the dependency of the convergence speed on the input signal power. The convergence and residual mean-square error characteristics of the different pipelined filters are compared

Translated title of the contribution	Pipelined DFE architectures using delayed coefficient adaptation
Original language	English
Article number	7
Pages (from-to)	868 - 873
Journal	IEEE Transactions on Circuits and Systems II - Analogue and Digital Signal Processing
Volume	45
Issue number	7
DOIs	https://doi.org/10.1109/82.700934
Publication status	Published - Jul 1998

Bibliographical note

Rose publication type: Journal article

Terms of use: Copyright © 1998 IEEE. Reprinted from IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, [see also Circuits and Systems II: Express Briefs, IEEE Transactions on]. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org.

By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

Keywords

adaptive filters
delayed least-mean-squares

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10.1109/82.700934

Perry IEEE CircuitsII July1998Accepted author manuscript, 203 KB

http://hdl.handle.net/1983/378

Cite this

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title = "Pipelined DFE architectures using delayed coefficient adaptation",

abstract = "In this paper the delayed least-mean-square (DLMS) algorithm is proposed for training a transversal filter-based decision feedback equalizer (DFE). Delays in the filter coefficient update process are used to pipeline the DFE, thereby increasing the throughput rate, for a given speed of hardware. The filter structures selected for the feedforward and feedback section of the DFE facilitate the use of a shared error signal, thereby reducing communication costs. The new resulting structure is highly modular and is very suitable for very large scale integration (VLSI) implementation. A pipelined form for the normalized least-mean-square algorithm (NMLS) is also obtained which removes the dependency of the convergence speed on the input signal power. The convergence and residual mean-square error characteristics of the different pipelined filters are compared",

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author = "R Perry and DR Bull and AR Nix",

note = "Rose publication type: Journal article Terms of use: Copyright {\textcopyright} 1998 IEEE. Reprinted from IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, [see also Circuits and Systems II: Express Briefs, IEEE Transactions on]. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. ",

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AU - Bull, DR

AU - Nix, AR

N1 - Rose publication type: Journal article Terms of use: Copyright © 1998 IEEE. Reprinted from IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, [see also Circuits and Systems II: Express Briefs, IEEE Transactions on]. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

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ER -

Pipelined DFE architectures using delayed coefficient adaptation

Abstract

Bibliographical note

Keywords

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