The structure, methodology and potential of a new design automation tool, POFGEN, for the generation of fixed function VLSI digital filters is described. The system accepts input data in the form of a coefficient vector and uses this to form a pipelined, multiplier-free architecture by employing primitive operator graph synthesis methods. The output from POFGEN is available either in the form of a structure diagram or as hardware description language (HDL) file for direct application specific integrated circuit (ASIC) generation
|Pages||631 - 634|
|Publication status||Published - May 1993|
Bibliographical noteSponsorship: The authors would like to thank Sony Broadcast and
Communications, the SERC and Dave Horrocks (UWCC)
for their support and assistance
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Name of Conference: International Symposium on Circuits and Systems
Venue of Conference: Chicago, IL, USA