POFGEN: a design automation system for VLSI digital filters with invariant transfer function

G Wacey; D R Bull

doi:10.1109/ISCAS.1993.393800

Abstract

The structure, methodology and potential of a new design automation tool, POFGEN, for the generation of fixed function VLSI digital filters is described. The system accepts input data in the form of a coefficient vector and uses this to form a pipelined, multiplier-free architecture by employing primitive operator graph synthesis methods. The output from POFGEN is available either in the form of a structure diagram or as hardware description language (HDL) file for direct application specific integrated circuit (ASIC) generation

Original language	English
Pages	631 - 634
DOIs	https://doi.org/10.1109/ISCAS.1993.393800
Publication status	Published - May 1993

Bibliographical note

Sponsorship: The authors would like to thank Sony Broadcast and
Communications, the SERC and Dave Horrocks (UWCC)
for their support and assistance

Terms of use: Copyright © 1993 IEEE. Reprinted from IEEE International Symposium on Circuits and Systems, 1993 (ISCAS '93).

This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected].

By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

Name of Conference: International Symposium on Circuits and Systems
Venue of Conference: Chicago, IL, USA

Access to Document

10.1109/ISCAS.1993.393800

Wacey IEEE ISCAS 1993Accepted author manuscript, 343 KB

http://hdl.handle.net/1983/1405

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Cite this

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abstract = "The structure, methodology and potential of a new design automation tool, POFGEN, for the generation of fixed function VLSI digital filters is described. The system accepts input data in the form of a coefficient vector and uses this to form a pipelined, multiplier-free architecture by employing primitive operator graph synthesis methods. The output from POFGEN is available either in the form of a structure diagram or as hardware description language (HDL) file for direct application specific integrated circuit (ASIC) generation",

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