Power/area analysis of a FPGA-based open-source processor using partial dynamic reconfiguration

SIH Zaidi, A Nabina, CN Canagarajah, JL Nunez-Yanez

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

3 Citations (Scopus)
534 Downloads (Pure)

Abstract

This paper explores the utilization of run-time partial dynamic reconfiguration in the LEON3 open-source soft core processor, which is a highly configurable SPARC (scalable processor architecture) V8 instruction set processor. The work explores the possibilities of sharing different arithmetic functions tightly coupled to the integer pipeline and mapped to the same silicon area, saving power consumption and area utilisation. The same strategy can be used to extend the instruction set architecture of the processor with new instructions that are optimized for DSP applications. The logic necessary to support these instructions could then be swapped as demanded by the application.
Translated title of the contributionPower/area analysis of a FPGA-based open-source processor using partial dynamic reconfiguration
Original languageEnglish
Title of host publicationEUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008 (DSD '08), Parma
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages592 - 598
Number of pages7
ISBN (Print)9780769532776
DOIs
Publication statusPublished - Sep 2008
Event11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008 (DSD '08) - Parma, Italy
Duration: 1 Sep 2008 → …

Conference

Conference11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008 (DSD '08)
CountryItaly
CityParma
Period1/09/08 → …

Bibliographical note

Conference Proceedings/Title of Journal: 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008 (DSD '08)
Rose publication type: Conference contribution

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