Processor with memory access stage adapted to fetch an instruction of a thread when no memory access operation is detected

David May (Inventor)

Research output: Patent

Abstract

A processor and method for executing threads. The processor comprises multiple instruction buffers, each for buffering the instructions of a respective associated thread, and an instruction issue stage for issuing instructions from the instruction buffers to a memory access stage. The memory access stage includes logic adapted to detect whether a memory access operation is defined in each issued instruction, and to fetch another instruction if no memory access operation is detected.
Original languageEnglish
Patent numberUS7958333
IPCG06F 9/30 9/40 13/00 13/28 3/00
Publication statusPublished - 7 Jun 2011

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