A processor and method for executing threads. The processor comprises multiple instruction buffers, each for buffering the instructions of a respective associated thread, and an instruction issue stage for issuing instructions from the instruction buffers to a memory access stage. The memory access stage includes logic adapted to detect whether a memory access operation is defined in each issued instruction, and to fetch another instruction if no memory access operation is detected.
|IPC||G06F 9/30 9/40 13/00 13/28 3/00|
|Publication status||Published - 7 Jun 2011|