TY - GEN
T1 - PSRR enhancement based on QFG techniques for low-voltage low-power design
AU - Valero, M. R.
AU - Ramirez-Angulo, J.
AU - Medrano, N.
AU - Celma-Pueyo, Santiago
PY - 2014/1/1
Y1 - 2014/1/1
N2 - A very simple power supply rejection ratio (PSRR) enhancement technique is presented. It is suitable, among others, for low voltage power low power (LVLP) DC circuits such as biasing circuits. It is shown that a high insensitivity to AC noise in supply rails can be achieved with an almost zero contribution to the total internal noise. This is achieved at the expense of very small additional circuitry and no additional power dissipation or supply requirements. Simulation and experimental verification of these characteristics is provided.
AB - A very simple power supply rejection ratio (PSRR) enhancement technique is presented. It is suitable, among others, for low voltage power low power (LVLP) DC circuits such as biasing circuits. It is shown that a high insensitivity to AC noise in supply rails can be achieved with an almost zero contribution to the total internal noise. This is achieved at the expense of very small additional circuitry and no additional power dissipation or supply requirements. Simulation and experimental verification of these characteristics is provided.
KW - Analog integrated circuits
KW - CMOS integrated circuits
KW - low-voltage low power design
UR - http://www.scopus.com/inward/record.url?scp=84907408629&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2014.6865726
DO - 10.1109/ISCAS.2014.6865726
M3 - Conference Contribution (Conference Proceeding)
AN - SCOPUS:84907408629
SN - 9781479934324
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2684
EP - 2687
BT - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
PB - Institute of Electrical and Electronics Engineers (IEEE)
T2 - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Y2 - 1 June 2014 through 5 June 2014
ER -