PSRR enhancement based on QFG techniques for low-voltage low-power design

M. R. Valero, J. Ramirez-Angulo, N. Medrano, Santiago Celma-Pueyo

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Abstract

A very simple power supply rejection ratio (PSRR) enhancement technique is presented. It is suitable, among others, for low voltage power low power (LVLP) DC circuits such as biasing circuits. It is shown that a high insensitivity to AC noise in supply rails can be achieved with an almost zero contribution to the total internal noise. This is achieved at the expense of very small additional circuitry and no additional power dissipation or supply requirements. Simulation and experimental verification of these characteristics is provided.

Original languageEnglish
Title of host publication2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages2684-2687
Number of pages4
ISBN (Print)9781479934324
DOIs
Publication statusPublished - 1 Jan 2014
Event2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
Duration: 1 Jun 20145 Jun 2014

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
CountryAustralia
CityMelbourne, VIC
Period1/06/145/06/14

Keywords

  • Analog integrated circuits
  • CMOS integrated circuits
  • low-voltage low power design

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