Pulse-based data transmission has been demonstrated as a power-saving and high performance alternative to level-based signalling over global distances. Key to its correct operation is the use of reliable and low latency pulse generators. We propose a simple design of pulse generator, evaluate its performance and show a design that offers greater safeguards against malformed input signals. We show how performance scales with interconnect length, consider signal-integrity issues and also present a method of repeating the signal to allow transmission over wire lengths exceeding 3 mm, and data rates exceeding 1Gbit/s. Results are presented by simulation as part of a a full pulse-based asynchronous Network-on-Chip. Simulation in a NoC context produces much more accurate results for factors such as delay than when simulating in isolation. Our simulations are carried out using a full RLC model, as opposed to the more common RC model. Inclusion of inductance further increases our result's accuracy, especially when compared to previous work. Finally, we see that the energy efficiency of our approach is comparable to other contemporary designs in the literature and is especially efficient over wire lengths in the range 1.25 mm to 3 mm.
|Translated title of the contribution||Pulse Generation for On-chip Data Transmission|
|Title of host publication||12th Euromicro DSD Conference on Digital System Design (DSD09)|
|Publication status||Published - Aug 2009|
Bibliographical noteConference Proceedings/Title of Journal: Proc. 12th Euromicro DSD Conference on Digital System Design (DSD09)
Conference Organiser: Euromicro