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Abstract
System-level reliability estimation is a crucial aspect in reliable design of embedded systems. Recently reported estimation techniques use separate measurements of power consumption and reliability to demonstrate the trade-offs between them. However, we will argue in this paper that such measurements cannot determine comparative reliability of system components with different power consumptions and hence a composite measurement of reliability and power consumption is required. Underpinning this argument, we propose a SystemC based system-level reliability analysis and estimation framework, RAEF, using a novel composite metric, power normalized reliability (PNR), defined as the ratio of reliability and power consumption. We show that PNR based estimation enables insightful reliability analysis of different system components. We evaluate the effectiveness of such estimation in RAEF using a case study of MPEG-2 decoder with four processing cores considering single-event upset (SEU) based soft error model. Using this setup, we analyze and compare PNR based estimation with existing reliability evaluations at different system hierarchies. Furthermore, we demonstrate the advantages of RAEF in assessing design choices highlighting the impact of voltage scaling and architecture allocation.
| Original language | English |
|---|---|
| Title of host publication | 2012 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI) |
| Place of Publication | NEW YORK |
| Publisher | IEEE Computer Society |
| Pages | 189-194 |
| Number of pages | 6 |
| ISBN (Print) | 978-0-7695-4767-1 |
| DOIs | |
| Publication status | Published - Jun 2012 |
| Event | IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI) - Amherst, Morocco Duration: 19 Aug 2012 → 21 Aug 2012 |
Conference
| Conference | IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI) |
|---|---|
| Country/Territory | Morocco |
| City | Amherst |
| Period | 19/08/12 → 21/08/12 |
Keywords
- MICROPROCESSORS
Fingerprint
Dive into the research topics of 'RAEF: A Power Normalized System-level Reliability Analysis and Estimation Framework'. Together they form a unique fingerprint.Projects
- 1 Finished
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PROCESS VARIATION AWARE SYNTHESIS OF NANO-CMOS CIRCUITS
Pradhan, D. K. (Principal Investigator)
1/10/09 → 1/03/13
Project: Research
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