RasP: An Area-efficient, On-chip Network

Simon Hollis, Simon W. Moore

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Abstract

We present RasP, our asynchronous on-chip network, which uses high-speed pulse-based signalling techniques. RasP offers numerous advantages over conventional interconnects, such as clock-domain crossing and skew tolerance. Most importantly, it features a very small global-wiring footprint. This compact nature allows a system designer to give priority to link bandwidth or signal-to-noise ratios, rather than being restricted by lane areas. We describe our point-to-point link and develop it into a fullyroutable system, with a repeater, router, arbiter and multiplexer. Simulations give throughput figures of between 1Gbits and 700Mbits in a 0.18 m technology, depending on interconnect length. We also show that it compares favourably in performance and area to Bainbridge et al.s Chain interconnect.
Translated title of the contributionRasP: An Area-efficient, On-chip Network
Original languageEnglish
Title of host publication24th International Conference on Computer Design (ICCD)
Publication statusPublished - 2006

Bibliographical note

Other page information: -
Conference Proceedings/Title of Journal: 24th International Conference on Computer Design (ICCD)
Other identifier: 2000797

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