Reducing the cost of implementing error correction codes in content addressable memories

Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, Marco Ottavi

Research output: Contribution to journalArticle (Academic Journal)peer-review

7 Citations (Scopus)

Abstract

Reliability is a major concern for memories. To ensure that errors do not affect the data stored in a memory, error correction codes (ECCs) are widely used in memories. ECCs introduce an overhead as some bits are added to each word to detect and correct errors. This increases the cost of the memory. Content addressable memories (CAMs) are a special type of memories in which the input is compared with the data stored, and if a match is found, the output is the address of that word. CAMs are used in many computing and networking applications. In this brief, the specific features of CAMs are used to reduce the cost of implementing ECCs. More precisely, the proposed technique eliminates the need to store the ECC bits for each word in the memory. This is done by embedding those bits into the address of the key. The main potential issue of the new scheme is that it restricts the addresses in which a new key can be stored. Therefore, it can occur that a new key cannot be added into the CAM when there are addresses that are not used. This issue is analyzed and evaluated showing that, for large CAMs, it would only occur when the CAM occupancy is close to 100%. Therefore, the proposed scheme can be used to effectively reduce the cost of implementing ECCs in CAMs.

Original languageEnglish
Article number6508821
Pages (from-to)432-436
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume60
Issue number7
DOIs
Publication statusPublished - 30 Apr 2013

Keywords

  • Content addressable memories (CAMs)
  • Error correction codes (ECCs)
  • Single error correction (SEC)
  • Soft errors

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