Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction

This paper presents an efficient technique for designing high defect tolerance Static Random Access Memories (SRAMs) with significantly low power consumption. The new approach requires drastically lower area overhead, simpler encoding and decoding algorithms, and zero fault-detection latency time for multiple error detection when compared to conventional techniques. The approach is based on the use of Built-In-Current-Sensors (BICS) to detect the abnormal current dissipation in the memory power-bus to improve the reliability of H-Tree SRAM memories. This abnormal current is the result of a single-event upset (SEU) in the memory, and it is generated during the inversion of the state of the memory cell being upset (bit-flip). We demonstrate the assertions of the proposed approach with HSPICE simulations, and a reliability analysis that combines BICS with single-parity bit (or Hamming codes) per SRAM word to perform error correction. Furthermore, the basic infrastructure provided by this approach can also be used to dynamically reconfigure the SRAM memory to save power, and to leverage fabrication yield.