Resuming thread to service ready port transferring data externally at different clock rate than internal circuitry of a processor

David May (Inventor), Peter Hedinger (Inventor), Alastair Dixon (Inventor)

Research output: Patent


A processor has an interface portion and an internal environment. The interface portion comprises at least one port. The internal environment comprises an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the interior portion and the at least one port in dependence on the first timing signal; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the thread scheduler being arranged to schedule the threads in dependence on the first timing signal. The port is arranged to transfer data between the port and an external environment in dependence on a second timing signal, and to alter a ready signal in dependence on the second timing signal to indicate a transfer of data with the external environment. The thread scheduler is configured to schedule one or more associated threads for execution in dependence on the ready signal.
Original languageEnglish
Patent numberUS7613909
IPCG06F 13/14
Publication statusPublished - 3 Nov 2009

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