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This paper investigates how a wide dynamic range of performance and power levels can be obtained in commercially available state-of-the-art hybrid FPGAs that include ARM embedded processors and independent power domains. Adaptive voltage and frequency scaling obtained with embedded in-situ detectors in a closed loop configuration is employed to scale performance and power in the FPGA fabric under processor control. The initial results are based on a high-performance motion estimation processor mapped to the FPGA fabric and show that it is possible to obtain energy savings higher than 60% or alternatively double performance at nominal energy. The available voltage and frequency margins in the device create a large number of performance and energy states with scaling possible at run-time with low overheads.
|Title of host publication||2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Number of pages||6|
|Publication status||Published - 17 Jul 2014|
|Event||2014 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2014 - Leicester, United Kingdom|
Duration: 14 Jul 2014 → 18 Jul 2014
|Conference||2014 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2014|
|Period||14/07/14 → 18/07/14|
- adaptive voltage scaling
- energy efficient design
- energy propotional computing
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