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Energy proportional computing (EPC) enables the allocation of energy to tasks depending on computational demands. Computing at full speed and then dynamically turning off modules when they are not required for a period of time can be used to obtain EPC and it is an alternative to voltage scaling techniques in which the computation is slowed down. This paper investigates the viability of physical power gating FPGA devices that incorporate a hardened processor in a different power domain. The run-time power gating approach is applied to Xilinx ZYNQ devices that incorporate a hardened Cortex A9 multi-processor. The paper demonstrates that power down followed by a full reconfiguration can be controlled by the embedded processor autonomously. The results show that the minimum time that the FPGA fabric must remain in power-off state for the technique to be energy efficient is in the order of milliseconds and up to 96% power reduction occurs when the fabric voltage is lowered below critical level. These results take into account the overheads of controlling the programmable voltage regulators interfaced to the FPGA and the overhead of the reconfiguration needed when the device must be returned to the active state.
|Title of host publication||Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Publication status||Published - 1 Jan 2014|
|Event||24th International Conference on Field Programmable Logic and Applications, FPL 2014 - Munich, United Kingdom|
Duration: 1 Sep 2014 → 5 Sep 2014
|Conference||24th International Conference on Field Programmable Logic and Applications, FPL 2014|
|Period||1/09/14 → 5/09/14|
- Energy Proportional Computing
- Power Gating
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