Run-time power modelling in embedded GPUs with dynamic voltage and frequency scaling

Jose Nunez-Yanez, Kris Nikov, Kerstin Eder, Mohammad Hosseinabady

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

1 Citation (Scopus)

Abstract

This paper investigates the application of a robust CPU-based power modelling methodology that performs an automatic search of explanatory events derived from performance counters to embedded GPUs. A 64-bit Tegra TX1 SoC is configured with DVFS enabled and multiple CUDA benchmarks are used to train and test models optimized for each frequency and voltage point. These optimized models are then compared with a simpler unified model that uses a single set of model coefficients for all frequency and voltage points of interest. To obtain this unified model, a number of experiments are conducted to extract information on idle, clock and static power to derive power usage from a single reference equation. The results show that the unified model offers competitive accuracy with an average 5% error with four explanatory variables on the test data set and it is capable to correctly predict the impact of voltage, frequency and temperature on power consumption. This model could be used to replace direct power measurements when these are not available due to hardware limitations or worst-case analysis in emulation platforms.

Original languageEnglish
Title of host publicationProceedings of the 11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures / 9th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2020
PublisherAssociation for Computing Machinery (ACM)
ISBN (Electronic)9781450375450
DOIs
Publication statusPublished - 21 Jan 2020
Event11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures / 9th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2020 - Bologna, Italy
Duration: 21 Jan 2020 → …

Publication series

NameACM International Conference Proceeding Series

Conference

Conference11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures / 9th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2020
Country/TerritoryItaly
CityBologna
Period21/01/20 → …

Bibliographical note

Funding Information:
This work was partially supported by the EPSRC ENEAC grant number EP/N002539/1, the H2020 TeamPlay project Grant agreement No.: 779882 and the Royal Society industrial fellowship MINET (Award: INF292044).

Publisher Copyright:
© 2020 Copyright held by the owner/author(s). Publication rights licensed to ACM.

Keywords

  • DVFS
  • Embedded GPU
  • GPU power modelling
  • Heterogeneous architecture
  • Multiple linear regression

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